Currently, in a process for manufacturing a CMOS FET device, as the size of the device becomes smaller, a sidespacer wall width applied as a hard mask for a deep source/drain ion implant also becomes smaller.
Thereby, the influence due to a lateral diffusion of the deep source/drain dopant is reflected in the electrical characteristics of the device (reduction in Vth and increase in leakage current).
In particular, in the case of a PMOS, since a deep source/drain ion implant process typically uses light boron, it is considered to be more fragile from the influence of the lateral diffusion from the deep source/drain, as compared to an NMOS.
Meanwhile, an attempt to reduce the channeling in a vertical or a depth direction has been made during implanting the dopant into the source/drain. In particular, a substrate is preamorphized by implanting ions vertical to the substrate into a desirable position. Such an ion implant is referred to as a preamorphization implantation.
As a result, a junction portion is made to be shallow in a vertical direction so that the short channel characteristic of the device is improved.
However, the junction depth is reduced to the size of about 30 nm or less, and any disadvantages due to the reduced junction depth may occur.
In other words, because of the reduced junction depth, dopant activity is restricted by means of silicide and the resistance (Rsd) of the source/drain is increased. The advantages obtained by the shallow junction are offset by means of the above disadvantages. Therefore, there is an increasing demand for a technology improving the scalability of the MOSFETs, in particular, the CMOS devices, in designing a ULSI (ultra large scale integrated) circuit without the problems and disadvantages in the related art such as the increase of the source/drain resistance and improving short channel characteristic including a threshold voltage (Vt) roll off.